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Integrated Circuit Systems, Inc.
Product Data Sheet
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
PIN ASSIGNMENT (9 x 9 mm SMT)
nDIF_REF1 GND REF_CLK DIF_REF0 nDIF_REF0 REF_SEL1 S_LOAD S_DATA VCC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M2006-11 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. It features serially programmable configuration of PLL frequency translation ratios, including FEC and inverse FEC. The device is similar to the M2006-04 (compatible pins and functions) but additionally provides automatic protection switching (APS) and automatic phase compensation functions.
DIF_REF1 REF_SEL0 ADD_CLK DROP_CLK NBW VCC DNC DNC DNC
28 29 30 31 32 33 34 35 36
M2006-11
(Top View)
18 17 16 15 14 13 12 11 10
S_CLOCK P1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
FEATURES
Integrated SAW (surface acoustic wave) delay line VCSO frequency from 300 to 700MHz (Specify center frequency at time of order) Low phase jitter 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) Similar to the M2006-04 (and pin-compatible), except adds APS (automatic protection switching) and APC APS narrows loop bandwidth when switching input references to maintain GR-253 MTIE and TDEV compliance APS is triggered by a > 4 ns clock phase change at input Automatic Phase Compensation (APC) function enables absorption of the input phase change. Narrow Bandwidth (NBW) control pin provides manual PLL control (set high for narrow bandwidth) Clock Add/Drop feature enables data FIFO centering Universal differential reference inputs support LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input Clock VCSO Output (MHz) Freq1 (MHz) Freq (MHz) 19.44 19.53125 622.08 625.00 622.08 155.52 156.25 Gigabit Ethernet Application
GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
OC-12/48
Table 1: Example Input / Output Frequency Combinations Using Power-up PLL Ratio
Note 1: Specify VCSO center frequency at time of order
Power-up default x32 multiplication ratio suitable for many optical networking applications Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M2006-11
NBW DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_CLK REF_SEL1:0 S_DATA S_CLOCK S_LOAD 2 P Divider 00 R Divider 01 1x M Divider FOUT0 nFOUT0 Serial Configuration Register FOUT1 nFOUT1 Loop Filter
VCSO
ADD_CLK DROP_CLK
P1
Figure 2: Simplified Block Diagram
M2006-11 Datasheet Rev 0.1
M2006-11 VCSO Based Frequency Translator with APS
Revised 29Apr2003
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Communications Modules
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M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12 13 15 16 17 18 20 21 22 29 23 24 25 27 28 30 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1 nFOUT1 FOUT0 nFOUT0 P1 S_CLOCK S_DATA S_LOAD REF_SEL1 REF_SEL0 nDIF_REF0 DIF_REF0 REF_CLK nDIF_REF1 DIF_REF1 ADD_CLK I/O Configuration Description
Ground Input Output Input Power Output No internal terminator
Power supply ground connections. External loop filter connections. See Figure 5,
External Loop Filter, on pg. 8.
Power supply connection, connect to +3.3V. Clock output pairs. Differential LVPECL. P Divider control. LVCMOS/LVTTL. For P1: Logic 1 sets divider to 4 Logic 0 sets divider to 1 See Table 5, P Divider Selection, on pg. 3 Serial input mode selection. LVCMOS/LVTTL. See Table 6, Serial Mode Function, on pg. 5 for how these three pins are used in combination. Reference clock input selection. LVCMOS/LVTTL. See Table 3, Reference Clock Input Selection, on pg. 3 Reference clock input pair 0. Differential LVPECL or LVDS.
Input
Internal pull-down resistor1 Internal pull-down resistors1 Internal pull-down resistors1 Internal pull-up resistor1 Internal pull-down resistor1 Internal pull-up resistor1 Internal pull-down resistor1
Input Input Input Input Input
Internal pull-down resistor1 Reference clock input. LVCMOS/LVTTL. Reference clock input pair 1. Differential LVPECL or LVDS.
Input
31 DROP_CLK
32 34, 35, 36
NBW DNC
Input
Increases M divider count by 1 for one phase detector cycle, which adds one extra VCSO clock cycle over time (clock slip). LVCMOS/LVTTL. Internal pull-down resistor1 Decreases M divider count by 1 for one phase detector cycle, which removes one VCSO clock cycle over time (clock slip). LVCMOS/LVTTL. See Table 9, Add / Drop Functions, on pg. 9. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN set to 2M Internal pull-up resistor1 . Logic 0 - Wide (normal) bandwidth, RIN set to 50k . Do Not Connect.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10.
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M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP OP_OUT RPOST nOP_OUT nVC VC SAW Delay Line
External Loop Filter Components
M2006-11
MUX
OP_IN Phase Detector RIN
nOP_IN
DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_CLK REF_SEL1:0
2
00
R Divider
R = 1-511 Power-Up Default = 1 RIN
01 1x
Loop Filter Amplifier
Phase Locked Loop (PLL)
Phase Shifter
VCSO
M Divider
M = 3-1023 Power-Up Default = 32 R8:0 M9:0
S_DATA S_CLOCK S_LOAD
FOUT0 nFOUT0 P Divider
P = 1 ( P1 = 0 ) or 4 ( P1 = 1 )
Serial Configuration Register
T2
FOUT1 nFOUT1
NBW
ADD_CLK
DROP_CLK
P1
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
Reference Clock Input Selection
REF_SEL1:0 Pin Settings (Pins 22, 29) 0 0 0 1 1 0 1 1 Reference Input Selection DIF_REF0, nDIF_REF0 DIF_REF1, nDIF_REF1 REF_CLK
Table 3: Reference Clock Input Selection
P Divider Selection
P1 Pin Setting (Pin 17) 1 0 P Divider Value 4 1 Output Frequency, FOUT1 (MHz) 155.52 622.08
M2006-11-622.0800
Table 5: P Divider Selector, Values, and Frequencies
Serial Programming M and R Divider Values *
Serial Settings per Bit Bits 210 T2:0 000 100 R8:0 876543210 000000001 . Definition
Bandwidth and Test Values
Normal Bandwidth * Narrow Bandwidth *
Feedback Divider Value "R"
Note: T1 and T0, used for test automation, must be set to 0
R = 1 minimum, power-up default R = 16 R = 511 M=3 M = 32 M = 1023 maximum minimum power-up default maximum
Note *: If either the T2 bit or the NBW pin is asserted (logic 1, HIGH), the device goes into Narrow Bandwidth mode. See also Figure 4, Serial Configuration Register, on pg. 5 and the subsection titled Narrow Bandwidth (NBW) Pin, on pg. 7.
. . . .
00010000 . 11111111 M9:0 9 8 7 6 5 4 3 2 1 0 0000000011 .
Reference Divider Value "M"
. . . .
0000100000 . 1111111111 M2006-11 Datasheet Rev 0.1
Table 4: Serial Programming M and R Divider Values
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M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet The PLL The PLL uses a phase detector and configurable dividers to synchronize the output of the VCSO with selected reference clock. The "M Divider" divides the VCSO frequency, feeding the result into the phase detector. The selected input reference clock is divided by the "R Divider". The result is fed into the other input of the phase detector. The phase detector compares its two inputs. It then outputs pulses to the loop filter as needed to increase or decrease the VCSO frequency and thereby match and lock the divider output's frequency and phase to those of the input reference clock.
M Divider, R Divider, and VCSO Frequency
FUNCTIONAL DESCRIPTION
The M2006-11 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of three selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). The M2006-11 will default to a multiplying factor of 32 on power-up. The multiplying factor can be changed by serially programming the input and feedback dividers by way of the serial programming register. A differential LVPECL signal provides the output clock for the device. A second differential output, which can be programmed to divide the output frequency by a factor of 4, is also available. The output frequency can be momentarily increased or decreased to add or subtract one net output clock cycle by asserting the ADD_CLK or DROP_CLK inputs, respectively. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. The frequency agility, bandwidth control, and protection switch features make the M2006-11 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in OC-3 through OC-192 applications. Input Reference Clocks One input reference clock is selected from among two differential LVPECL clocks and one single-ended LVCMOS / LVTTL clock. The maximum input frequency is 700MHz. The input reference clock is selected from DIF_CLK 0, DIF_CLK 1, or REF_CLK by selecting the appropriate REF_SEL0 and REF_SEL1 inputs.
The relationship between the VCSO (Fvcso) frequency, the M and R dividers, and the input reference frequency (Fref_clk) is: M Fvcso = Fref_clk x -------R The ratio of M/R times input frequency must be such that it falls within the "lock" range of the VCSO. On power-up the M and R dividers are set to 32 and 1, respectively. The M divider (10-bits) can be programmed for a maximum value of 1023 and a minimum value of 4. The R divider (9-bits) can be set to a maximum value of 511 and a minimum value of 1. P Divider and Outputs The M2006-11 provides a total of two differential LVPECL output pairs: FOUT0 and FOUT1. FOUT0 operates at the VCSO frequency while FOUT1 can operate at the VCSO frequency (Fvcso) or 1/4 Fvcso.
For example, FOUT1 can output 155.52MHz while FOUT0 outputs 622.08MHz.
One output divider (the "P" divider) is for the FOUT1 output pair. The P divider divides the VCSO frequency to produce one of two output frequencies (Fvcso or 1/4 Fvcso). The P1 pin selects the value for the P divider: logic 1 sets P to 4, logic 0 sets P to 1.
See Table 5, P Divider Selection, on pg. 3.
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Serial Configuration Register The M2006-11 is serially programmed by way of a three-wire interface, with the inputs being S_DATA, S_CLOCK, and S_LOAD. When S_LOAD is LOW, configuration data is serially loaded from S_DATA into the Serial Configuration Register (or "shift register") with the rising edge of S_CLOCK. The T2 bit is loaded first, M0 last. (See point "a" in the timing diagram: "Figure 4, Serial Programming Timing Diagram," below.) The contents of the shift register are loaded in parallel into the R and M dividers when S_LOAD transitions to HIGH (at point "b" in the timing diagram.) The divider values are "latched" when S_LOAD transitions to LOW again (at point "c" in the diagram). This means the divider values remain loaded and unaffected by any serial input. (If S_LOAD is held HIGH, any S_DATA input is passed directly to the R and M dividers on each rising edge of
S_CLOCK.) Serial Programming Timing Diagram
S_DATA T2 T1 T0 R8 R7 R6 R5 R4 R3 R2
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
See also: - Table 6, Serial Mode Function, below - Figure 9, Setup and Hold Time, on pg. 12
R1
R0
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK S_LOAD a bc
Points a, b, and c used in section "Serial Configuration Register" above. T1 and T0, which are used for test automation, must be set to 0. T2 is set to 1 for normal bandwidth, 0 for narrow bandwidth. (If either NBW pin or T2 is asserted, device goes into Narrow Bandwidth mode.)
Figure 4: Serial Programming Timing Diagram
Serial Mode Function Pa
L = Low; H = High; X = Don't care; = Rising Edge Transition; = Falling Edge Transition
S_LOAD S_CLOCK S_DATA Conditions
L L L L H X
Data Data Data X Data
Serial input mode. Shift register loads state of S_DATA on each rising clock of S_CLOCK. (However, serial input does not affect the values in the R and M dividers.) Entire contents of the shift register are passed (in parallel) to the R and M dividers. R and M divider values are latched. Serial input does not affect the values in the R and M dividers. Serial input affects dividers: S_DATA passed directly to R and M dividers as it is clocked.
Table 6: Serial Mode Function
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Automatic Protection Switch (APS) The M2006-11 includes a proprietary automatic protection switch (APS) circuit that prevents excessive phase transients of the output clocks upon input reference rearrangement. Upon the occurance of an input reference phase change, or phase transient, PLL bandwidth is lowered by the APS circuit. This limits the rate of phase change in the output clocks. With proper configuration of the external loop filter, the output clocks will comply with MTIE (maximum time interval error) specifications for GR-253 (SONET) and ITU G.813 (SDH) during input reference clock changes. The APS circuit uses a dedicated phase error detector at the PLL phase detector to detect a clock phase change. During normal operation with a stable reference clock, the PLL will be frequency locked and phase locked, resulting in very little error at the phase detector (<1 ns). Upon the selection of a new input reference clock at a different clock phase, a phase error will occur at the phase detector. The APS circuit is triggered with a phase error greater than 4 ns, upon which a narrow PLL bandwidth is applied. When the PLL locks to within 2 ns error at the phase detector, wide bandwidth (normal) operation is resumed. The APS circuit is not suitable for situations in which an unstable reference is used. Under normal conditions the reference clock jitter should not induce phase jitter at the phase detector beyond 2 ns. (This includes when subjecting the system to jitter tolerance compliance testing.) Because of this, the M2006-11 is not recommended for use with some Stratum DPLL clock sources, or with unstable recovered network clocks intended for loop timing configuration. It is also not recommended for complex FEC ratios where the phase detector is operated at less 1 MHz. For these applications the M2006-04 is suggested. (The M2006-04 is identical to the M2006-11 except that it does not include the APS function or the APC function discussed in the following section.)
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet Automatic Phase Compensation (APC) The M2006-11 also includes an automatic phase compensation (APC) circuit that is automatically enabled in conjunction with the APS circuit. The APC circuit enables the PLL to absorb most of the phase change of the input clock which reduces re-lock time and also the generation of wander. (Wander is created in this case by the generation of extra output clock cycles.) The APC circuit is triggered by same >4 ns phase transient (at the phase detector) that triggers the APS circuit. Once triggered, a new VCSO clock edge is selected for the phase detector feedback input. (The clock edge selected is the one closest in phase to the new input clock phase.) The residual phase detector phase error following reselection is approximately 3-to-4 ns. The narrow bandwidth selected by the APS circuit minimizes VCSO drifting and switch transients during the process.
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Narrow Bandwidth (NBW) Pin The M2006-11 includes a manual narrow bandwidth (NBW) setting that can be selectively enabled by asserting the NBW input (pin 32) to logic 1. When the NBW pin is logic 0, the M2006-11 operates in the nominal wider bandwidth mode.
If either NBW pin or the serially programmed T2 bit is asserted (logic 1, HIGH), the device goes into Narrow Bandwidth mode. See Table 4, Serial Programming M and R Divider Values, on pg. 3 and Figure 4, Serial Configuration Register, on pg. 5
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet The NBW pin is useful for two main applications:
*
NBW can be selectively asserted high to manually
*
assert and hold a temporary narrow loop bandwidth operation during the phase locking to a newly selected clock reference input. When configured with the right loop filter component values, this can assure that M2006-11 clock output slew rate is sufficiently decreased to meet GR-253-CORE MTIE and TDEV. NBW can be tied to logic 1 to permanently enable lower loop bandwidth which might be preferred for a given jitter attenuation application.
Loop Bandwidth Calculator A free loop bandwidth calculator is available.
Call 508-852-5400, ICS Communications Modules business unit (CMBU), Worcester, MA.
In relation to the APS circuit, the NBW setting functions as follows:
* Setting NBW to logic 1, the NBW function overrides the
APS circuit to force narrow bandwidth mode.
* Setting NBW to logic 0, the APS circuit can
automatically turn on and off narrow bandwidth mode. The NBW pin operates by controlling the values of RIN, an internal loop filter component as illustrated in Figure 3, pg. 3. In normal operation when NBW is set to logic 0, RIN = 16k When NBW is asserted to logic 1, RIN is . increased to 2M .
NBW Pin Setting (Pin 32) 0 1 Internal Value RIN 1 50k 2M PLL Configuration (Loop Bandwidth) Normal Loop Bandwidth Narrow Loop Bandwidth
Table 7: NBW Pin Settings
This calculator can be used to determine the loop filter values needed to obtain a desired loop bandwidth and damping factor. Pass band peaking can also be calculated. The calculator is also useful for understanding the effect of the NBW selection on loop filter characteristics.
Note 1: With the same set of loop filter components
Compared to normal operation (when pin NBW = logic 0), setting NBW to logic 1 does the following:
* Loop bandwidth is decrease by a factor of 40 * Loop damping factor is decreased by a factor of 6.3
Indiscriminate use of the NBW pin can lead to an under damped loop configuration. A loop damping factor of >0.5 should be maintained to assure stable loop operation.
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External Loop Filter To provide stable PLL operation, and thereby a low jitter output clock, the M2006-11 requires the use of an external loop filter components. These are connected to the provided filter pins (see Figure 5). Due to the differential signal path design, the implementation consists of two identical complementary RC filters as shown in Figure 5, below.
RLOOP CLOOP RPOST CPOST CPOST RLOOP OP_IN
4 9
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
CLOOP OP_OUT
8 5
RPOST nOP_OUT nVC
6 7
nOP_IN
VC
Figure 5: External Loop Filter
PLL bandwidth is affected by the "M" value as well as the VCSO frequency. See Table 8, External Loop Filter Component Values, on pg. 8. External Loop Filter Component Values 1 M2006-11-622.080
VCSO Parameters: KVCO = 800kHz/V, VCSO Bandwidth = 70kHz
Device Configuration FRef (MHz) 19.44 19.44 19.44 155.52 155.52 FPhase Detector (MHz) 19.44 19.44 19.44 155.52 155.52 M NBW RIN Divider Pin Value 0 50k 622.08 32 2M 1
(MHz)
FVCSO
Example External Loop Nominal Performance Using Filter Component Values These Values R loop C loop R post C post PLL Loop Damping Passband Bandwidth Factor Peaking
(dB)
39k 150k 910 15k 2k
0.10F 0.10F 10F
20k 82k
220pF 15pF
3.4kHz 115Hz 14kHz 310Hz 770Hz 20Hz 10kHz 338Hz 1.4kHz 40Hz
4.4 0.7 16.77 2.7 10 1.6 4.7 0.75 6.3 1
0.1 2.2 0.001 0.25 0.02 0.5 0.1 2.0 0.05 1.25
622.08 622.08 622.08 622.08
32 32 4 4
0 1 0 1 0 1 0 1
50k 2M 50k 2M 50k 2M 50k 2M
100k 220pF 15pF 220pF
0.10F 100k 10F 50k
Table 8: External Loop Filter Component Values
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and Passband Peaking.
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Add / Drop Clock The ADD_CLK and DROP_CLK inputs increment or decrement the M (feedback) divider on the rising edge of the Add or Drop clock for one phase detector cycle. This results in a momentary increase or decrease in output frequency and an extra or missing VCSO output clock cycle (clock slip) relative to the input reference clock. The ADD_CLK (pin 30) and DROP_CLK (pin 31) inputs are intended to be used for pointer realignment in the data channel FIFO register. The assertion of either pin imparts a single VCSO cycle slip over time. The rate at which the cycle occurs is determined by the loop filter bandwidth, which is influenced by the external loop filter components selection (see Table 8, External Loop Filter Component Values, on pg. 8).
Adding One Clock Cycle When ADD_CLK is transitioned from low to high, one extra
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
Dropping One Clock Cycle
The DROP_CLK pin works the same way, except that when this pin transitions from to low to high, the feedback counter is decremented by one count which subtracts one VCSO output clock over time.
How Assertions Affect the Add / Drop Functions Both ADD_CLK and DROP_CLK modify the M Divider
following the next rising edge of the reference clock into the phase detector (the R Divider output). Only one ADD_CLK assertion or DROP_CLK assertion can be made per phase detector clock cycle. Additional assertions during a given phase detector cycle will be ignored. Additional assertions prior to phase detector realignment will accumulate as additional phase detector error, and will cause further VCSO frequency offset.
An accumulated offset of over 4 nsec will trigger the APS mode, which will lower the loop bandwidth accordingly until the phase error is less than 2 ns. How Output Divider Affects the Add / Drop Functions
clock will be output by the VCSO relative to the reference input. This is accomplished by incrementing the feedback divider (M Divider) by one count for one phase detector cycle period (one R Divider output cycle). This incrementing of the feedback divider creates an immediate error at the phase detector input equal to one VCSO clock cycle. In the process of relocking the phase of the M Divider output to the R Divider output, the PLL forces the VCSO frequency to slightly increase (several ppm) and then decrease once locked. The net effect is a single "cycle slip" of the VCSO over several milliseconds. A VCSO frequency of 622.08MHz represents a cycle time of 1.6 nsec, which is the phase error imparted on the phase detector with one ADD_CLK command.
The rate of cycle slip is controlled by the loop bandwidth during normal operation as listed in Table 8. The APS circuit, which lowers loop bandwidth following an input transient over 4 ns, is not invoked unless is there is also high phase noise on the reference clock input.
The divider block (P Divider) between the VCSO output and the FOUT1 clock output pair also influences the effect of ADD_CLK and DROP_CLK assertions relative to the FOUT1 output. When P1 is low (forces P Divider = 1) the ADD_CLK or DROP_CLK pin will add or subtract one entire clock cycle upon a single assertion (this is always true for the FOUT0 output clock pair). When P1 is high (forces P Divider = 4) the ADD_CLK or DROP_CLK pin will add or subtract one quarter of a clock cycle upon a single assertion, as would be expected by the clock division.
Add / Drop Functions Pa
X = Don't care; = Rising Edge Transition
ADD_CLK
DROP_CLK Conditions
X X
Adds one extra clock cycle to the VCSO clock output, over time, when asserted. Subtracts one clock cycle to the VCSO clock output, over time, when asserted.
Table 9: Add / Drop Functions
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M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter Rating Unit
VI VO VCC TS
Inputs Outputs Power Supply Voltage Storage Temperature
-0.5 to VCC +0.5 -0.5 to VCC +0.5
4.6
V V V
oC
-45 to +100
Table 10: Absolute Maximum Ratings
Note 1:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings ard stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter Min 3.135 0 Typ 3.3 Max 3.465 Unit
VCC TA
Positive Supply Voltage Ambient Operating Temperature
V
oC
+70
Table 11: Recommended Conditions of Operation
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3 Volts + 5%, TA = 0 oC to 70 oC, VCSO Frequency = FOUT = 622-675MHz, Outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min 3.135
Typ 3.3 162
Max 3.465
Unit
Power Supply VCC ICC Differential Inputs LVCMOS / LVTTL Inputs Inputs with Pull-down VP-P VCMR VIH VIL IIH IIL IIH IIL Rpullup All Inputs Differential Outputs Cin VOH VOL VP-P
Positive Supply Voltage Power Supply Current Peak to Peak Input Voltage Common Mode Input Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Input Low Current Internal Pull-up Resistor Input Capacitance Output High Voltage Output Low Voltage Peak to Peak Output Voltage
FOUT_0, nFOUT_0, FOUT_1, nFOUT_1 All Inputs nDIF_REF0, nDIF_REF1, NBW (All Inputs except nDIF_REF0, nDIF_REF1, NBW) DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 P1, S_LOAD, S_CLOCK, S_DATA, REF_SEL0, REF_SEL1, REF_CLK, ADD_CLK, DROP_CLK, NBW
V mA V
0.15 0.5 2 Vcc - .85 Vcc + 0.3 0.8
V V V A A k
-0.3
150 -5
51
Rpulldown Internal Pull-down Resistor Inputs with Pull-up -150
5
51 4 Vcc - 1.4 Vcc - 2.0 0.6 Vcc - 1.0 Vcc - 1.7 0.85
A A k pF V V V
Table 12: DC Characteristics
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M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3 Volts + 5%, TA = 0 oC to 70 oC, VCSO Frequency = FOUT = 622-675MHz, Outputs terminated with 50 to VCC - 2V
Symbol Parameter
Min DIF_REF0, nDIF_REF0, DIF_REF1, nDIF_REF1 S_CLOCK REF_CLK 0.3 0.3
Typ
Max 700 50 200 175
Unit Test Conditions
FIN
Input Frequency
MHz MHz MHz MHz MHz ppm dBc/Hz Fin=19.44_MHz dBc/Hz M=32, R=1 dBc/Hz ps ps P1 = 0 or 1 % ps
20% to 80%
FPD FOUT APR n
Phase Detector Frequency Range Output Frequency Range VCSO Pull-Range Single Side Band Phase Noise @622.08MHz Jitter (rms) Output Duty Cycle
1
FOUT0, nFOUT0, FOUT1, nFOUT1
75
700
120
1kHz Offset 10kHz Offset 100kHz Offset 12kHz to 20MHz 50kHz to 80MHz 40
P1 = 0
200 -72 -94 -123
0.5 0.5 50 275 60 400
J(t) odc tR
Output Rise Time for FOUT0, nFOUT0 and
FOUT1,nFOUT1
1
200
tF tS tH tLOCK tIPW
Output Fall Time 1 for FOUT0, nFOUT0 and
FOUT1,nFOUT1
P1 = 0
200 5 5 5 5
275
400
ps ns ns ns ns ms ns ns ns
20% to 80%
Setup Time Hold Time PLL Lock Time Input Pulse Width
1
S_DATA to S_CLOCK S_CLOCK to S_LOAD S_DATA to S_CLOCK S_CLOCK to S_LOAD S_LOAD ADD_CLK DROP_CLK
100 10 10 10
MTIE
Mean Time Interval Error
Compliant with GR-253-CORE
Table 13: AC Characteristics
Note 1: See Parameter Measurement Information on pg. 12.
M2006-11 Datasheet Rev 0.1 Integrated Circuit Systems, Inc.
11 of 14 Communications Modules
Revised 29Apr2003 w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
PARAMETER MEASUREMENT INFORMATION
Input and Output Rise and Fall Time
80% Clock Inputs 20% and Outputs
80% VSWING 20% tF
tR
Figure 6: Input and Output Rise and Fall Time
Output Duty Cycle
nFOUT
FOUT tPW (Output Pulse Width) tPERIOD odc = tPW tPERIOD
Figure 7: Output Duty Cycle
Differential Input Level
VCC - 0.85 nDIFF_CLK VPP DIFF_CLK Cross Points VCMR
Setup and Hold Time
tHOLD + 0.5 tSET-UP
Figure 8: Differential Input Level
Figure 9: Setup and Hold Time
M2006-11 Datasheet Rev 0.1 Integrated Circuit Systems, Inc.
12 of 14 Communications Modules
Revised 29Apr2003 w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Figure 10: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
For VCSO Frequency (MHz) 622.08 Order Part Number
M2006-11-622.0800
Table 14: Ordering Information
Consult ICS for the availability of other VCSO frequencies.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
M2006-11 Datasheet Rev 0.1 Integrated Circuit Systems, Inc.
13 of 14 Communications Modules
Revised 29Apr2003 w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
M2006-11 Datasheet Rev 0.1 Integrated Circuit Systems, Inc.
14 of 14 Communications Modules
Revised 29Apr2003 w w w. i c s t . c o m
tel (508) 852-5400

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